pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL: Parser, Dataflow Analyzer, Controlflow Analyzer and Code Generator
v1.3.0by Shinya Takamaeda-YamazakiApache License 2.0
AI Health Summary — Claude-generated analysis of download trends, maintenance, and risk signals.
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Based on latest version 1.3.0. If you're running an older version, check OSV for your specific version.
Exclude CI/CDPRO
Best Day
726
May 8
Worst Day
329
Apr 26
Peaks On
Thus
670 avg
Quietest
Suns
488 avg
Download Trend
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